Wafer direct bonding is based on the short range intermolecular attraction forces at the bonding interface. Wafer bonding and layer transfer technology is VLSI compatible, highly flexible and manufacturable. It appears that two solid-state plates of almost any materials can be directly bonded to each other at room temperature provided that their surfaces are sufficiently smooth, flat and clean. Combined with generic layer thinning methods, transfer of almost any layer onto any substrate may be possible. Not only can integrated materials be made, but also 3-D devices and 3-D SOC may be developed. The major challenge appears to be wafer bonding and layer cutting at low or room temperature that retain integrity of the layer. Innovative low temperature wafer bonding technologies have shown that room temperature covalent bonding and low temperature epitaxial or hetero-epitaxial-like bonding are feasible. It is likely that wafer bonding and layer transfer technology will be an indispensable part of future integrated circuit or system-on-chip fabrication processes, similar to diffusion, oxidation and photolithography technologies in today's semiconductor industry.

The physical mechanisms involved in the Smart Cut^® process have been extensively studied. The splitting, obtained by thermal treatment, is linked to cavity growth by an Ostwald ripening mechanism and crack propagation due to the total stress applied to the structure. The splitting kinetics are controlled by hydrogen diffusion. Results indicate that splitting can occur in semiconductors such as Si, SiC, GaAs and InP, but also in LiNbO₃. Other studies report that Ge, GaN, LaAlO₃ and SrTiO₃ can also be split after hydrogen implantation. The ability to obtain thin films by the Smart Cut^® process combined with specific bonding via thermally conductive or metallic layers has also been demonstrated. In this chapter we focused essentially on homogeneous thin film transfer but previous studies have shown that this process is also compatible with patterned layers. The Smart Cut^® process is a breakthrough in material engineering, offering new material and structures to the industry where enabling materials are in high demand.

SOI wafer characterization is built on the arsenal of characterization techniques developed for bulk Si and many techniques can be applied without modification. For layer thickness measurement and surface inspection, the SOI layer structure introduces complications which require modified or specialized equipment. By far the greatest challenge lies in the electrical characterization of the top Si layer for which the ψ-MOSFET technique is workable but still a slow and cumbersome procedure.

Silicon-on-silicon bonding is an operation of ultra-fine alignment, joining and thermal bonding of two wafers, namely 'handle' and 'device' substrates. Prior to the joining step, both wafer substrates are ultra-clean in terms of surface haze and sub-micron particulate contamination. Each pre-join silicon wafer surface is 'hydrophilic'. The thermal annealing operation is performed using a 'wet' oxidation step at elevated temperatures. The effectiveness of bonding is dependent upon the degree of hydrophilicity as well as surface flatness. The quality of the interface layer within a bonded pair is evaluated in terms of density of voided or disbonded regions as well as electrical yield. The density of micro-voids within an interface layer is directly dependent upon light point defect density of the pre-join substrates. The shape of the spreading resistivity profile carrier map is an indicator of the electrical quality of the interface layer. Detailed manufacturing data collected over a period of eighteen months are presented.