High Speed Data Converters
High speed data converters represent one of the most challenging, important and exciting analog and mixed-signal systems. They are ubiquitous in our modern and highly connected world. Understanding and designing this class of converters require proficiency in analog circuit design, digital design, and signal processing. This book covers high speed data converters from the perspective of a leading high speed ADC designer and architect, and with a strong emphasis on high speed Nyquist A/D converters. Topics covered include an introduction to high-speed data conversion; performance metrics; data converter architectures; sampling; comparators; amplifiers; pipelined A/D converters; time-interleaved converters; digitally assisted converters; evolution and trends The book is intended for engineers and students who design, evaluate or use high speed data converters. A basic foundation in circuits, devices and signal processing is required. The book is meant to bridge the gap between analysis and design, theory and practice, circuits and systems. It covers basic analog circuits and digital signal processing algorithms. There is a healthy dose of theoretical analysis in this book, combined with the practical issues and intuitive perspectives.
Inspec keywords: analogue-digital conversion; comparators (circuits); amplifiers
Other keywords: time-interleaved converters; amplifiers; pipelined A/D converters; high speed data converters; digitally assisted converters; performance metrics; data converter architectures; comparators
Subjects: A/D and D/A convertors; A/D and D/A convertors; Other digital circuits; Amplifiers; General electrical engineering topics; General and management topics; Other analogue circuits
- Book DOI: 10.1049/PBCS026E
- Chapter DOI: 10.1049/PBCS026E
- ISBN: 9781849199384
- e-ISBN: 9781849199391
- Page count: 464
- Format: PDF
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Front Matter
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1 Introduction
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In this chapter we discussed the A/D and D/A conversion processes. The A/D conversion is comprised of sampling and quantization operations. The D/A conversion is comprised of an analog holding operation followed by a reconstruction filter. The analysis of each one of these operations was presented. In addition, the Nyquist sampling theorem was discussed, together with the concepts of undersampling and oversampling. Finally, the decimation and interpolation operations were covered.
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2 Performance metrics
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In the previous chapter, we discussed ideal A/D and D/A conversion. Practically, there are numerous non-idealities that make the conversion process deviate from the ideal. In this chapter, we discuss the metrics used to characterize the converter's performance, with a focus on high speed ADCs. Since there are multiple dimensions of performance, the characterization of an A/D converter can be a complicated, and sometimes even confusing, process. For an ADC designer or user, it is imperative to understand the various performance metrics, and their relationship with one another.
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3 Data converter architectures
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In this chapter, we discuss some high speed ADC architectures, which include the flash, pipelined, and time-interleaved ADCs. In addition, architectures that were historically used in low speed applications, such as successive approximation (SAR) and delta-sigma converters, are covered because of their recent resurgence in the high speed space. Some DAC architectures, such as the resistive, capacitive, and current steering DACs, are also discussed.
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4 Sampling
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This chapter discusses the challenges of input sampling in high speed ADCs. The focus is on the design trade-offs and optimizations that enable high performance and can lead to further improvements in the future. It presents discussions and analyses of the non-linear behavior of the sampling circuits. They are meant to illustrate trends and behaviors in a simple and intuitive way, which necessitated making some assumptions and approximations, while avoiding overly complex mathematical analysis that may be more rigorous, but less insightful.
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5 Comparators
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Comparators are omnipresent in A/D converters. Every ADC has at least one comparator, and the quantization operation is performed by comparators. A comparator generates a digital output bit that depends on the relation between its two inputs. A full flash converter is simply a group of comparators that quantize the input signal by comparing it to a set of equidistant thresholds. There are numerous comparator architectures; some of which represent profoundly different trade-offs, while others tend to be largely similar in their performance. In this chapter, we discuss comparators with a focus on the architectures and design techniques that are often used in state-of-the-art high speed ADCs. The principles, design parameters, and trade-offs will be covered.
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6 Amplifiers
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In this chapter, the structure, analysis, and design of amplifiers are discussed. Amplifiers are used as sample-and-hold circuits (SHAs), as inter-stage (MDAC) amplifiers in pipelined ADCs, and in the integrators of sigma-delta converters. The performance of the amplifier is often critical for the whole ADC. For example, in a pipelined ADC, the MDAC's amplifier is the main building block that determines the performance and speed of the ADC's quantizer. If a feedback amplifier drives a capacitive load or a switched capacitor circuit, it can use an operational transconductance amplifier (OTA). If it drives a resistive load, it needs to use a low impedance operational amplifier (opamp). However, for simplicity, the “opamp” term is often used to describe both kinds of amplifiers.
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7 Pipelined A/D converters
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In spite of its limitations, the pipelined ADC architecture still runs supreme as the dominant architecture for high speed and high resolution ADCs. Through different incarnations and modifications, such as incorporating SAR ADCs in a pipelined ADC structure, using different methods of amplification and employing digital assistance, it has managed to survive and flourish. Moreover, by taking advantage of interleaving, it is well suited to continue to enjoy a prominent place in the high speed and high performance converter space.
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8 Time-interleaved converters
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The time-interleaved (TI) architecture is an attractive choice when achieving the desired sampling rate is not possible or efficient with a single ADC. Time-interleaved ADCs were first introduced in 1980 by Black and Hodges [1]. In principle, they enable high sampling rates by using multiple ADC channels in parallel. However, the inter-channel mismatches have traditionally limited the performance of this class of converters to low resolutions. Recently, there has been a resurgence of interest in time-interleaved ADCs to push the state of the art in performance, speed, and power consumption. This has been driven by the need for higher sampling rates while facing practical limits and prohibitive costs in process technology. In this chapter, we cover the analysis, performance limitations, and some implementation approaches of time-interleaved ADCs. We augmented the theoretical analysis with an intuitive and practical perspective. However, the analysis is needed to understand the operation of this class of converters and to enable the understanding and development of methods and algorithms to improve their performance.
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9 Digitally assisted converters
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In this chapter, the authors discussed some of the advanced calibration techniques used in pipelined and time-interleaved ADC. These techniques represent the state-of-the-art in digitally assisted ADCs. They enable higher sampling rates, higher performance, lower power consumption, and better integration in fine lithography CMOS processes. It is important to note that the field of digitally assisted converters is an active area of research with developments and breakthroughs occurring at a fast pace. This chapter is meant to present a snapshot of the state of the art with some of the most effective techniques. The common theme is that there are a lot of limitations and active problems to solve. The field of digitally assisted converters is nowhere where it needs to be. So, analog designers should not worry about being obsolete yet.
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10 Evolution and trends
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Over the past two decades, impressive progress has been made in the high speed and high resolution ADC space. The sampling rate and bandwidth have increased at an astounding pace. The resolution and linearity have improved to levels previously unimaginable. The input frequency has skyrocketed to reach the GHz range, and the clock jitter has been reduced to less than 50 fs. This progress has been accomplished while keeping the power consumption roughly the same, if not lower. These advancements were driven in part by the explosive growth in wireless communications and the unquenchable thirst for more bandwidth, higher performance, and lower power to accommodate our smart phones, tablets, laptops, entertainment, and numerous other applications. In this chapter, the authors discuss the evolution of the high speed ADC space over the past two decades, while emphasizing trends and future directions. In addition to the overall view of the high speed space, we will focus on the evolution of the high speed and high resolution ADC subspace from the author's experience and perspective.
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Back Matter
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