In this chapter, technology development, based on projections of new and emerging TCAD tools and methodologies, that offers exciting opportunities in realising new paradigms for the design-manufacturing interface is presented. It is important to have a better interface between process and product designers that will provide both sides with an understanding of how choices affect the overall chip performance, reliability and yield. As this new interface is created and explored, TCAD tools will find a new relevance in the IC design community. This will create new opportunities for innovation for TCAD research. The role of TCAD in compact model development was also presented.

In this chapter, a brief discussion on the nature of point defect-mediated diffusion, boron diffusion in silicon and SiGe, and reasons for strain relaxation in SiGe has been made. Because of the relationship between dopant diffusion and point defect diffusion.both the movement of point defects and dopants need to be modelled simultaneously. It has been shown that boron in strained, low Ge-composition SiGe layers diffuses primarily via an interstitial mediated mechanism. Mobile misfit dislocations can act as a strong interstitial sink but immobile dislocations appear to have very little effect on the point defect population. However, experiments should be performed to determine the segregation coefficient across the Si/SiGe interface as a function of germanium and dopant concentration. Further studies should also be taken up to find more closely the relationship between relaxation and interstitial absorption.

The use of TCAD to investigate design and applications of devices based on SOI technology has been reviewed. SOI technology allows integration of high performance innovative devices that can push forward the present frontiers of the CMOS downscaling. As one moves from 0.1 μm generation and below, SOI offers a number of advantages in low power, communication circuits and system-on-chip and may ultimately replace bulk CMOS technology. SOI technology improves per formance over bulk CMOS technology by 25-35 per cent, equivalent to two years of bulk CMOS advances and offers the low power advantages. Indeed some perceived SOI disadvantages (self-heating, hot carriers and early breakdown) are no longer such a significant problem for operation at low voltage. The importance of using strained-Si alongside SOI technology to yield significant improvements in mobility has been highlighted.

A retrospective look at the development and production of SiGe HBTs reveals that significant challenges have been overcome to make SiGe now a mature technology. In this chapter, key developments including the SiGe epitaxial growth process, overall integration methods, and elimination of yield-limiting defects to enable production of highly integrated products have been presented. Optimising the interaction of the EPI layer with its surroundings has enabled the achievement of high bipolar device yield. Integration of HP SiGe HBT with CMOS logic and a host of passive devices has created technologies that are well suited for a broad range of HP communication products. Modular integration approaches, such as the base-after-gate approach, has simplified the development of SiGe HBT technologies. It is observed that use of a modular integration approach enables a quick migration to next generation and derivative technologies easily. Enhancements have been achieved primarily in cost reduction, increased integration, and application specific voltage/power requirements. Vertical SiGe HBTs compatible with SOI CMOS have been discussed. The unique feature of collector voltage pinning in thm Si film was discussed in depth, which gives rise to high breakdown voltage, high Early voltage, and low collector capacitance. The SOI device is promising for a better fT-BV_ceo trade-off than that from conventional collector scaling in bulk devices. The fabricated devices show the anticipated strong dependence of d.c. and RF characteristics on SOI substrate bias. IBM's and IHP's SiGe and SiGeC BiCMOS technologies that have driven the requirements for the most advanced communication applications have been discussed. As a TCAD example, process and device simulation results for a trench isolated double polySiGe HBT using the process simulator ATHENA and device simulator ATLAS towards SiGe/SiGeC technology development have been presented. Use of TCAD tools for the SiGe/SiGeC technology development is expected to offer the process and device designers significant advantages in time-to-market, cost, power and performance prediction.

The aim of this chapter has been to provide a background for bipolar compact modelling. The main improvements of the VBIC model over the SGP model is the addition of Early voltage effect, quasi-saturation, substrate parasitic, avalanche multiplication, self-heating and modelling of the parasitic pnp transistor. A methodology to extract and optimise d.c. and a.c. parameters for the VBIC model is developed and applied to SiGe HBTs. The model has been verified and optimized using a VBIC pseudo-code and an excellent agreement has been found. A comparison of the VBIC and SGP model clearly illustrates the weakness of the conventional SPICE Gummel-Poon model when applied to advanced SiGe HBTs. The MEXTRAM model includes a direct coupling between current and charge, thus leading to coupled d.c. and a.c. behaviour. This has the advantage of a physical representation of the device, which facilitates accurate scaling. The MEXTRAM and VBIC bipolar transistor models are comparable for low and medium collector current densities and frequencies. Parameter conversion from MEXTRAM to VBIC can easily be done for the depletion capacitances and d.c. parameters related to low and medium current levels. HICUMs major advantages over other bipolar models are its scalability, simple and process-based/related parameter extraction, predictive capability of process and layout variations, and simple numerical formulation. TCAD tool TRADICA has also been discussed. ANFIS automates RF modelling as it is technology independent, neuro-computing based, intelligent and capable of achieving any predetermined accuracy limit required.

Analog, mixed-signal and RF continue to be a challenge for digital CMOS designers and manufacturers. The performance is ultimately limited by the accuracy of the passive components in the technology. Conflicting scaling methodologies, complex measurement and modelling support requirements, a multiplicity of interacting features and increasingly complex process integration issues are the challenges to overcome to support the next generation of product designs. The ability to accurately construct and model passives with Qs > 15-20 at frequencies > 10 GHz represents a key enabler for new circuits and products.