The aim of this book is to present the FGMOS transistor as a powerful device from the circuit design point of view. The inputs in the transistor, significantly more numerous compared with the normal MOS device, appear as extra degrees of freedom which the designer has to play with in order to get a desired functionality. Hence, by establishing the right relationships between them, it is possible to achieve design tradeoffs that are not viable with conventional MOS devices, especially in a context in which power consumption and supply voltage are the main design constraints.

The FGMOS transistor can be seen either as a MOS transistor with an analog adder circuit connected at its gate, or as an MOS transistor with an electrically tunable threshold voltage, or even as a complex nonlinear multiplier divider block. Besides the degrees of freedom the designer now has to play with increases from 3 to N + 2 for a single device, where N is the number of inputs in the FGMOS. This opens up a new range of possibilities for the designer in terms of design tradeoffs. Although this is very promising, designing becomes even more complex. This chapter has illustrated with simple examples how to obtain the benefits of the FGMOS. In addition, an overview has been given on how to foresee when the device might or might not be useful in different contexts, all of them having in common the low power constraint.

This chapter presents filter designs that use the characteristic features of the FGMOS transistor operating in the strong inversion saturation region to be able to operate at a very low power supply voltage with also a very low power consumption. The chapter also analyses the drawbacks of using FGMOS transistors and based on this analysis advises the reader on when not to use them. Thus, for example it shows how in certain cases, the PSRR can be seriously degraded, and if it is a design constraint the transistor should be used in a different way, or even avoided. Finally, the chapter also describes what happens when the input capacitances in the FGMOS transistors are realised in metal/poly instead of poly2/poly 1, using as an example the second integrator/filter block. The purpose is to illustrate what would occur in those cases in which only purely digital technologies are available.

This chapter described how to use FGMOS transistors to design internally nonlinear and externally linear logarithmic filters. It has been shown how very compact realisations can be designed by using the inputs in the transistor for different purposes, such as tuning, signal processing, biasing and control of the common mode. Because of this there is no need of stacking transistors to implement translinear loops, which simplifies the design under the low-voltage constraint apart from having other added advantages that have also been explained along the chapter. The main disadvantage of these realisations is related to the parasitic couplings to the FGs in the FGMOS devices that together with the mismatch increase the distortion levels. In general though this kind of topology performs very well in low frequency, low accuracy applications in which the main design constraints are power and low supply voltage.

This chapter summarises the most relevant results and conclusions that have been presented throughout the book. Chapter 2 focused on the characterisation and modelling of the FGMOS transistor. Chapter 3 introduced basic circuit blocks that illustrated some of the interesting features of the FGMOS transistor. Chapters 4 and 5 demonstrated the potential of FGMOS devices biased in the strong inversion region for the design of low power and low voltage programmable analog Gm-C filters. Chapters 6 and 7 explored the design of low power and low voltage Gm-C and log-domain filters, taking advantage of the functionality of the FGMOS transistor biased in the weak inversion saturation region and using the translinear principle, which was reformulated for the FGMOS. Finally, Chapter 8 moved away from analog design, illustrating the advantages of using FGMOS devices in digital circuits.