Cellular radio telephone handsets are now in common use throughout the world. The resultant commercial pressure for compact and low-cost products has led to renewed global research interest in receivers and the consequent development of highly integrated solutions based on architectures that might otherwise have languished as mere curiosities. The resultant widespread acceptance of zero-IF (intermediate frequency) and low-IF receivers in handsets for GSM (Global System for Mobile communications) has taken integration to a level from which any further signif icant improvement is now hard to imagine. But the additional need to address new, third-generation (3G) standards, such as UMTS (Universal Mobile Telecom munication System), is tending to re-focus research activities in this area towards increased flexibility and the maximisation of hardware re-use. This is most easily addressed by increasing the level of digitisation. However, unless this is handled intelligently, power consumption can easily be increased over and above that used by existing analogue implementations, with unacceptable consequences in terms of battery life. Hence, we present a novel architectural solution to this problem, mainly in the context of GSM but which forms part of a multimode receiver for both GSM and UMTS.

This chapter overviews field programmable analogue array (FPAA). General concepts, architectures, design issues, circuit techniques and applications of FPAAs are presented. Commercial FPAAs are reviewed and a CMOS OTA-C FPAA is described. The concepts of field programmable mixed-signal array (FPMA) and systems on a programmable chip are also introduced. Potential applications of FPAAs and FPMAs in wireless communications are discussed. The chapter is organised in the following way. Section 4.2 is concerned with generic concepts, architectures, design issues, advanced circuit techniques, and general applications of FPAAs. Section 4.3 overviews commercial FPAA products with different bandwidths and circuit tech niques. The design and implementation of a continuous-time high-frequency CMOS OTA-C FPAA is then presented in Section 4.4. Section 4.5 introduces the concepts of FPMA and systems on a programmable chip (SoPC). Potential applications of FPAA and FPMA in universal transceivers are described in Section 4.6. Finally, Section 4.7 concludes the chapter with some future research perspectives of the FPAA and FPMA.

This chapter is divided into the following sections. Section 6.2 discusses requirements for filters in the context of fully integrated wireless transceivers, and the need for on-chip tuning systems. Section 6.3 describes methods of filter implementation. Different filter architectures including the second-order cascade, multiple loop feedback and ladder simulation are described. The most widely used techniques for filter implementation include the OTA-C and MOSFET-C techniques. The increasing operating frequency of integrated wireless transceivers and availability of on-chip inductors has led to the development of active-LC techniques. Section 6.4 discusses issues connected with filter tuning, including the difficulties introduced by circuit parasitics. Different methods of implementing filter tuning systems are outlined. Section 6.4.6 examines the special difficulties involved in tuning high-Q, high frequency filters, and describes a proposed tuning technique for the leap-frog class of bandpass filter. The chapter is summarised in Section 6.5.

There are several obstacles which make the implementations of a PA very difficult in CMOS technology. The use of submicron CMOS increases the difficulty of implementation due to technology limitations such as low breakdown voltage and poor transconductance. However, with the trend of lower power transmitters in the next generation, implementation of CMOS PAs with good efficiencies are becoming realistic despite steadily declining FET breakdown voltages.

In this chapter, some of the techniques, challenges and recent developments in the test and characterisation of RF, analogue, and mixed-signal circuits have been described. Specifically, present test techniques were introduced and shown to rely on direct access methods using external test equipment. These methods require the synchronisation of different pieces of measurement apparatus and rely on excessively long interconnection media for electronic signal delivery to/from the device being tested.Such a measurement paradigm is becoming increasingly infeasible as modern mixed signal devices continue to require tight measurement specifications and higher test signal bandwidths while offering a reduced number of interface pins for direct exter nal access. Thus, although clever test list ordering and optimisation can be employed, some fundamental changes to test access methods have to be sought. To tackle this problem, this chapter introduced new techniques that can significantly enhance the testability and diagnostic ability of mixed-signal integrated circuits. At the heart of these techniques is a highly robust, compact, scalable and easily synthesisable embed ded test core that emulates the functions of fully-fledged production-phase automatic test equipment. The integration of such a core represents a radical change from the present test practice; however, it is envisioned to provide a practical solution to an impending problem facing the semiconductor industry.