This chapter has addressed some topics in g_m-C filter design. Two integrator loop, LC ladder-based and multiple loop feedback OTA-C filter structures have been studied. Design examples using a wideband high output resistance OTA have been presented. Current-mode g_m-C filters have been discussed and compared with voltage-mode counterparts. Tuning issues including both analogue and digital schemes have been discussed.

The advent of highly integrated wireless transceivers is a platform for the research and development of active LC filters on silicon chips. The design of such filters presents great challenges to designers. The quality of on-chip reactive components is the main reason for this, since the losses and the parasitics in those components can result in frequency response distortion, and the need for active components, like negative resistors, limits dynamic range. Nevertheless, the performance already achievable may be sufficient for the implementation of such filters in certain parts of the transmitter, e.g. at the output of mixers, where a large signal must be bandpass-filtered. Many improvements are needed, and can be expected in the future, in the realisation of higher quality on-chip inductors and capacitors, in filter synthesis when the reactive component losses are large, in the accurate compensation of such losses using negative resistances, in the implementation of those resistances with low noise and high linearity, and in the automatic tuning of on-chip active LC filters.

We have established a viable approach for low voltage filters using the switched current technique. First, we showed that switched currents, unlike switched capacitors, suffer no performance degradation as the supply voltage is lowered. When the supply reaches about IV, class AB switched currents can be expected to outperform switched capacitors.

We have in this chapter presented the main ideas that have been proposed in the literature for the tuning of integrated continuous-time filters. To minimise interference problems, master-slave schemes are used most often. Although first-order master stages have been employed, typically, second-order filters or oscillators are used because they can be matched more reliably to second-order slave filter stages. Even for that case, matching of much better than 1 percent between master and slaves on a chip is difficult to maintain. This problem increases at higher frequencies when parasitic components become more important. Whether the master-slave technique or a direct tuning method is used in cases where the filter has periodic inactive periods, it is helpful for better matching and tracking that a filter architecture is chosen that has many identical circuit blocks. The tuning algorithm will be simpler and the control circuitry smaller, less noisy and less power-hungry DFT is a well understood and accepted requirement in integrated circuits, i.e. an IC is 'designed for test'. Analogously, it is crucial for success that an integrated analogue filter is 'designed for tuning'. The filter topologies must be tunable, must be insensitive to parasitics, and be constructed with well matched circuit blocks. The unavoidable overhead penalty for tuning will then be minimised.