This chapter is a broad overview of the problems of testing circuits of VLSI complexity and systems into which they may be assembled. As will be appreciated, the testing problem is not usually one of fundamental technical difficulty, but much more one of the time and/or the cost necessary to undertake a procedure which would guarantee 100% correct functionality. The subsequent chapters of this text will therefore consider the types of failures which may be encountered in microelectronic circuits, fault models for digital circuits, the problems of observability and controllability and the various techniques that are available to ease the testing of both digital and mixed analogue/digital circuits. Finally, the financial aspects of testing which reflect back upon the initial design of the circuit or system will be considered, as well as the production quantities that may be involved. We will conclude this chapter with a list of publications which may be relevant for further general or specific reading. The more specialised ones may be referenced again in the following chapters.

This chapter considers several strategies for generating tests for digital circuits which, with the noticeable exception of I _DDQ testing involve the monitoring of the 0 and 1 primary output response to appropriate input test vectors. By far the greatest development effort has been concerned with combinational logic. Roth's D-algorithm forms the basis of many automatic test pattern generation programs, but the computational effort in producing ATPG programs for the increasing size and complexity of present-day VLSI circuits is becoming prohibitive. This has forced an increasing interest in other means of test pattern generation, which usually involves some partitioning of the circuit at the design stage so as to allow exhaustive, non exhaustive or pseudorandom test patterns to be used.

Because of the difficulties or complexities encountered when formulating acceptable tests for integrated circuits as they become larger and more complex, it is now essential to consider testing at the design stage of a VLSI circuit or system using VLSI parts, and not as an afterthought once the design has been completed. The old-fashioned separation between a design engineer who designs a circuit or system and a test engineer in a separate office who takes the design and then attempts to formulate an acceptable test strategy for it is no longer viable. Design for testability, sometimes called design for test and almost always abbreviated to DFT, is therefore the philosophy of considering at the design stage how the circuit or system shall be tested, rather than leaving it as a tack on exercise at the end of the design phase.

This chapter has ranged rather summarily over the testing requirements of autonomous analogue-only circuits and A-to-D and D-to-A converters, the vast majority of which will be off the shelf standard parts or standard designs. The difficulty is the very wide diversity of circuits and applications involved, see Figure 7.5, and the detailed specialist knowledge of analogue circuit design which is necessary to discuss the specification, the design and the tolerancing of most circuits in any depth. Also, all analogue circuits have an acceptable tolerance of performance in the time and frequency domain which must be part of the testing specification for the circuit, and hence simple deterministic go/no-go tests are difficult to formulate.As we have seen, functional testing of such circuits is the norm, using commercial instrumentation to generate test inputs and monitor test response. The vendor will inevitably be highly involved in the production testing of standard parts, using considerable resources and in-house expertise; the OEM will generally be involved in less comprehensive functional tests of individual components or parts.

The overall importance of costing does not need emphasising, since it is the responsibility of every vendor and OEM not to make a financial loss across their range of products. Microelectronic costs, however, may be difficult to assess, and may be based upon previous experience rather than on precise financial data relating to a new product. Within the theme of this text, namely testing, it would clearly be cheaper for an IC vendor not to test production wafers and finished ICs, and for an OEM not to test a final product; on the other hand it is clearly equally unacceptable to subject every manufactured product to lengthy exhaustive life tests.

The following gives the positions in n-stage autonomous cellular automata of the type 150 cells necessary to produce a maximum-length sequence of 2ⁿ - 1 states. All remaining cells in the n-stage string of cells are the simpler type 90 cells.