This book draws together tutorial contributions from experts in industry and academia to provide, for the first time, a fairly comprehensive text devoted to covering key technologies in this diverse and exciting emerging field. The book is organised in four parts, namely: i) process technology, ii) device modelling/characterisation and circuit simulation, iii) reliability and test, and iv) circuit and system design methodology. Although the main emphasis of each chapter justifies its placement in a particular part, as much integration of device, process and design knowledge as possible has been sought for each contribution. In this chapter a few enabling developments are briefly introduced, driven by an emphasis on emerging radio frequency (RF) or wireless techniques, and including some considerations for engineering education, technology transfer and innovation.

Process and device simulation is commonly used for the design of new VLSI technologies. Simulation programs serve as exploratory tools in order to gain better understanding of process and device physics. On the other hand, simulations are also carried out after the design phase to optimise certain parameters of a technology, e.g., to improve device performance and reliability or to increase the yield. For all these tasks the term TCAD, short for technology computer-aided design, was coined. TCAD includes both physically rigorous as well as simplified process and device simulation in one to three spatial dimensions. Furthermore, links to layout-oriented CAD and circuit simulation are required.

Stanford's approach to low-voltage CMOS shows that, without speed performance loss, significant power reductions are achieved after modifying CMOS processes to accommodate low, tuneable thresholds. A key concept is to balance the leakage power of inactive circuits with the switching power of the circuits doing the work. This requires electrical adjustment of threshold voltages and new circuit design techniques. Electrically tuneable thresholds can accommodate a wide range of applications and activity levels in a system, and can significantly improve worst case performance at low voltage. Well and substrate ties are separated from supply rails and controlled to compensate for process and ambient variations. An implementation of a self tuning system using low/tuneable threshold devices in a VLSI environment was shown. For the same switching speed, fabricated devices show significant reduction in switching power when compared to standard devices operated at a higher supply voltage. Cryogenic ULP techniques allow for insight into deep submicron effects and allow the same performance of standard 5V CMOS to be achieved at 330mV, for 1/230 of the energy. The key to high performance at low voltage is low or near-zero threshold. This requires room temperature thresholds of about -200mV for maximum performance at 77K. ULP techniques are only in their infancy and yet they have already provided a very good opportunity for increased levels of interaction among process, device, circuit and system engineers towards optimum low power microelectronic solutions.

This chapter reviews the characteristics of the most important SOI materials, as well as the key features of the SOI MOSFET. Prospective applications are described, particularly in the field of low-voltage, low-power integrated circuits. The potential offered by new devices, such as lateral SOI bipolar transistors, microwave SOI MOSFETs, and quantum-effect SOI devices, is also presented.

The goal of this chapter is to provide insight into the radiation effects involved in space and high energy physics environments. These environments can cause significant damage to spacecraft or detector electronics. They can cause degradation through total-dose ionising radiation damage, single event related soft and hard errors, and displacement damage. Sensitivity and performance of commercial technologies have been discussed with respect to Silicon-On-Insulator (SOI) for these radiative environments. Description and results of an SOI technology called DMILL have been also reported. DMILL technology is expected to fulfil the constraints of high energy physics electronics and could be of interest in other fields, such as space, military, and nuclear power applications, where radiation tolerant integrated circuits are required. Other potentialities for this SOI technology are its use in communication applications due to its high transistor performance, or in micromachining for sensor readout on the same chip. Therefore, we think that both device and circuit designers will find this an interesting development area, and a good example of process-device-design interaction for the manufacturability of microsystems.

This chapter describes various III-V semiconductor FET characterisation and modelling techniques. Two new techniques for implementing large-signal models in SPICE have permitted the development of a new MESFET model, which is not only realistic but also runs more quickly. These techniques address continuity for distortion and intermodulation analysis, and rate-dependent and thermal transient behaviour. The model has accuracy extended over a range of operating conditions that is obtained by inclusion of secondary aspects of device operation. Accuracy is obtained with improved device characterisation to fit behavioural trends of device operation. In many applications this is more important than simply fitting traditional I-V and S-parameter measurements (see for instance Chapter 24). Fast, large-signal pulse measurements are considered as more suitable for characterising devices.

This chapter presents a fully analytical MOS transistor model dedicated to the design, analysis and simulation of low-voltage and/or low-current analogue circuits.

A major problem of large signal compact modelling of bipolar transistors (BJT) at radio frequencies is the inconsistency of the static and dynamic behaviour of the model. The quasi-static assumption is not accurate, and the physical operation of a BJT has many different modes. It is difficult to find a compact equivalent circuit topology which is valid for all regions of operation such as low injection, high injection, avalanche breakdown, saturation and quasi-saturation. A smooth transition from one region to another maintaining charge conservation and continuous derivatives of the non-linear circuit functions becomes a major problem. In practice, the classical SPICE Ebers-Moll (SEM) and Gummel-Poon (SGP) models with minor dynamic extensions are widely used in radio frequency design including heterojunction bipolar transistor (HBT) circuits. A summary of these models and of one new large signal BJT model, VBIC95 is given.

A versatile circuit design tool has been described. It has been shown that the simple nodal DC analysis of circuits having only independent or linear voltage controlled current sources is adequate for simulating the most complicated practical circuits or systems. The object-oriented programming style has been exploited to create a compact software tool, the properties of which can be expanded afterwards without touching the original source code. The total amount of code including all models and properties described in this chapter is less than 4 Mbytes both in UNIX and Windows environments. The price paid for the adoption of object orientation is slightly reduced speed. To do exactly the same operations in traditional procedural programming means direct memory manipulation while in object-oriented programming, additional function calls with message-passing are needed (Figure 9.2). On the other hand, object orientation offers many more possibilities to provide advanced functionality. Object orientation also opens up new vistas in algorithm development since control of the algorithms is brought down from the system level to the individual models composing the system equations.

This chapter has summarized practical aspects of key analog and analog/digital interaction problems: Sources of noise; Methods of coupling; Effects of power distribution on chip noise; Effect of substrate referencing on coupled noise; Effects of chip signal isolation/shielding techniques on noise; Effect of package on noise; and Effect of card layout and circuit topology on noise. Techniques related to semiconductor processing; circuit architecture and design; chip floorplanning; chip wiring; design systems; packaging that enhances control or reduction of undesired analog or analog/digital interaction in mixed signal and analog monolithic ICs were surveyed. Consideration was given to substrate coupling, power rail and I/O driver resonances, near field capacitive and inductive as well as package interaction. Spe cial attention was given to distribution of substrate contacts and how the substrate is referenced in highly doped substrates. Actual hardware experiences along with techniques, methodologies, and strategies for analog mixed signal noise reduction were shared. Data results on noise isolation achieved and performance of an actual hardware along with what special techniques were used was discussed. For a more detailed treatment of this subject and software algorithms Reference is an exhaustive treatment of this subject and presents a method for rigorous simulation of the substrate effects.

This chapter introduces a new method for the analysis and optimisation of reliability as an integrated part of the design process of electronic circuits and systems. It bases itself on the analysis of the susceptibility of failure mechanisms in components as a function of the combinations of external stress factors (stressor-sets). The chapter describes the background of stressor-susceptibility analysis, the need for this analysis and the way this method is used for high-level design and optimisation of electronic circuits. The theory is illustrated using the example of secondary breakdown in a (power) bipolar semiconductor, which can be applied, for instance, in 'smart power' designs. The methodology introduced can also be applied in systems of non-electronic and/or mixed nature.

This chapter presents an investigation of design and manufacturing practices on the reliability of electronic devices, circuits and systems, with a strong focus on monitoring techniques to estimate the impact of these practices. Reliability models of these devices and systems have generally relied heavily on statistical data collected over a long period of time and codified into standards by various governments, technical agencies and companies. While new approaches to reliability analysis and modelling are emerging, some standards are still widely applicable. However, they barely cover new generations of devices designed and manufactured with new techniques such as ASIC designs, quick prototyping using array technologies, ever-changing semiconductor manufacturing methods, new packaging procedures, etc.

This chapter describes test strategies, including a concise introduction to DSP testing, for analog and mixed-signal circuits. The main emphasis will be on integrated circuits. Although design-for-testability and design-for diagnosibility are only briefly reviewed, two self-test schemes for mixed-signal ICs are presented in more detail describing the necessary components along with implementations for the on-chip generation of test stimuli . Some prerequisites for automatic fault simulation of analog circuits are dealt with. Fault models for analog circuits are discussed and the local layout realistic faults mapping scheme which allows more realistic fault models to be obtained prior to the final layout is introduced. Appropriate simulation fault models are discussed along with a brief description of the automatic fault simulation tool AnaFAULT and the fault extraction tool LIFT.

This chapter discusses the potential of CMOS and BiCMOS to obtain high speed and low power. It demonstrates that CMOS technologies of today have the ability to approach 1 GHz clock frequencies. By combining CMOS with bipolar transistors, using a BiCMOS process, we may combine very high data rates (< 40 Gb/s) and very high complexity (using CMOS) in a single chip. It discusses the possibility to reduce power in CMOS circuits and showed that considerable power reduction can be obtained by sacrificing clock frequency (not necessarily sacrificing computing capacity). Also demonstrates the possibility to reduce power considerably, with no or very little reduction in clock frequency through process reoptimisation. These results may be interesting enough to affect process generations coming along. Finally it discusses the future development of CMOS technology and concluded that CMOS has very much more to give.

This chapter discusses design methodologies for ultra-low-power (ULP) CMOS circuits at different abstraction levels, namely system, architectural, logic, design, and layout. The main techniques to reduce power consumption are introduced such as reduction of circuit activity, operating frequency, switched capacitances and supply voltages. Low-voltage and low-power techniques for microprocessors are reviewed, including cache and interleaved memories. Previous chapters have introduced ULP techniques and possibilities for advanced processes with extremely low supply and threshold voltages. This chapter exploits techniques to achieve ULP consumption without aggressively changing processes. Many opportunities for reducing power consumption at a given throughput are opened by appropriately combining the ULP techniques presented here.

This chapter describes the matched delay technique and its applications. First, the fundamental concepts of matched delay design are described. Next, we discuss several practical issues that must be considered in matched delay system designs. Finally, three fabricated designs using the matched delay technique are presented. The matched delay technique was employed in developing a high-performance digital sampler with 1 Gbit/s bandwidth and 25ps resolution in a MOSIS 1.2μm CMOS process. The matched delay sampler implements the demultiplexing function of a network interface by performing a serial-to-parallel conversion on an incoming data stream. In addition, this device is a core component in another matched delay design, a data recovery circuit.

The use of the modified flexible statistical models for MOS and BJT allows the designer to incorporate the parameter variations in any nominal model deck. Therefore, the transistor parameters need not be re-extracted if a different nominal model is used. In addition, the important MOS transistor and BJT parameters for statistical simulation are identified. The strength of circuit simulation based on the modified flexible statistical model is its ability to estimate the performance variance of a given circuit without prior knowledge of the circuit performance. Therefore, the simulation model and methodology are not performance or circuit topology limited. This feature is important when a new design is simulated statistically . However, the simulations provided by the model do not yield information as to which transistor contributes to the performance variance. In order to enhance the capability of the modified and the original flexible statistical models, a sensitivity analysis (derived from the two factorial design for experiment technique) for the effect of parameter mismatch on circuit performance is developed. The sensitivity analysis provides an efficient way to detect the effect of each transistor mismatch on the circuit performance. Together with the flexible statistical model, it is proven useful in the analysis and design of precision analog and mixed-mode integrated circuit.

Over the past decade there has been a continual increase in the high frequency/high-speed potential of operational amplifiers, and these improvements in performance have been made possible, in part, by the development of new fast complementary BJT process technologies. The availability of fast vertical PNP transistors as well as NPNs has breathed new life into the performance of conventional voltage op-amps. In addition, the development of complementary BJT technology has also led to the emergence of a range of operational amplifiers which make use of current feedback rather than conventional voltage feedback. The concept of “current-feedback” is not a new idea, and can in fact be traced back to the early days of cathode feedback. However the circuit design symmetry required to implement these high-speed architectures has meant that the technique has only really become practical for fully-integrated implementation with true complementary BJT processing.

This chapter reviews some recent design developments in Analog-Sampled-Data Signal Processing (ASD SP). Following a brief review of the state-of-the-art in switched capacitor (SC) signal processing, the “current mode” switched-current (SI/S²I) technique is presented. New techniques for exploring niches in low voltage, low current, tuneable systems or very high speed BiCMOS and GaAs circuits are introduced with reference to current work, and some design suggestions are given for further circuit implementations. The S²I technique is maturing quickly offering a potential cost/performance advantage for single-chip mixed mode systems implemented in standard digital ULSI/VLSI technologies.

In this chapter, the Infopad project has a long term goal of providing a system solution to the problem of accessing information from high bandwidth networks in a portable wireless manner. Optimisations are being made at all levels, extending from the circuit design in the portable units, through to the protocols on the high speed backbone networks. We are finding that significant advantages can be gained from this unified approach, which could not be achieved by independent efforts at the various network levels. The next generation of Infopad will support multiple users, cells and applications.

This chapter reviews the contributions of ICs for the RF front-end of wireless receivers and transmitters operating in broadcast and personal communication bands. Various design styles, architectures and levels of integration in different technologies are compared, combining process, device, and design knowledge for increased manufacturability.

Over the past several years, wireless communications have seen dramatic advances in two distinct areas. On one hand, the demand for portable voiceband services has resulted in intense research efforts to improve performance and increase capacity through digital transmission. Such systems focus on wide-area narrowband communications, providing low-bandwidth network services to individual users in a portable fashion. On the other hand, the need for more flexible computer networks has led to the advent of wireless LANs such as the Motorola Altair. Such systems focus on local-area wideband communications, providing networking services to individual computers but usually they are not easily portable. However, the distinction between these two systems is rapidly blurring. As laptop computers place mobile computing resources in the hands of individuals, wireless technologies capable of providing wide-area, wideband services will clearly be needed. With this merging of computation and communications, individual users will have instantaneous and portable access to fixed information networks via a lightweight mobile unit. Furthermore, users will be capable of transferring data to other users and accessing fixed computing resources without any constraints on where or when such access takes place. As shown in the figure, the mobile unit will support a myriad of services, including full-motion digital video and high-quality audio data, and combine the functionality of today's analog mobile telephones, radio pagers, and laptop personal computers.

This chapter has discussed the design of various types of receiver mixers, starting with basic discrete forms, then moving on to classical topologies. The benefits of emitter degeneration to improve linearity were quantified, after which we showed the advantages afforded by the bipolar 'multi-tanh' concept. This circuit concept has been extensively used by the author, and is now proving useful in extending the dynamic range in many contemporary communications ICs. Multi-tanh gm stages have the further advantage of allowing accurate variable gain through the control of the bias current, not possible with many mixer designs. Finally, the topic of noise in the switching core was briefly discussed. Other novel mixer topologies are now being used to extend the performance of active mixers even further. In the future, it is expected that quite different approaches to mixer design, based on sub-micron CMOS processes, will become commonplace, though it is difficult to forecast whether (and if so, how soon) such techniques will eclipse bipolar technologies in RF applications. With increasing interest in short-range transceivers operating at frequencies of between 2 and 30GHz, and the benefits of heterojunction bipolar transistors in this domain, it will be interesting to see how this age-old rivalry will develop.

This chapter have briefly studied distortion mechanisms in short channel FETs. We have identified a number of topologies and situations where device circuit interaction can lead to crippling levels of frequency dependent distortion. The common source amplifier was found to be immune to this effect. It has shown how the 2-port nature of the transconductance non-linearity of a short channel MESFET can lead to nulls in distortion with load and bias. Predicting the location of these nulls places an unprecedented demand on model accuracy. It has found that the Parker Skellern MESFET model provides a satisfactory guide to the nature of the load and bias dependence of distortion. The design principles described are also applicable to other IC technologies presented in this volume.

In this chapter we discuss the state-of-the-art and current trends in the design of intelligent low-cost high-performance sensor systems. In intelligent (sensor) systems the best of conventional ideas are upgraded and combined with good new ideas. Therefore, there is a continuous growth in the amount of cleverness embedded in the designs. This continuous growth is accompanied by a discontinuous growth pattern attributable to breakthroughs. Breakthroughs are brought about, for instance, by the introduction of new low-cost high-performance products, such as PCs, software packages, integrated circuits, microcontrollers, smart sensors and smart interfaces, and by new technologies, such as micromachining and thin-film technology.

The smart-sensor era has only recently started (see Chapter 25). However, there is already a wide variety of smart sensors and systems available. In this chapter we will discuss a number of sensor principles, designs and applications in two important sensor groups: thermal sensors and capacitive sensors. The terms 'thermal' and 'capacitive' refer to signals of the intermediate type only, and not to the physical input or output signals themselves. Yet, as will be shown, there is a lot of similarity in the signal processing for the various types of sensors within a certain group. Besides the sensor groups dealt with in this chapter, there are other important groups, such as optical, chemical and magnetic sensors. However, it is the aim of this text to show a design philosophy and methodology rather then to give a complete survey.