High throughput sonar processors
The performance of the next generation of operational sonars must be improved to counter the effects of target noise reduction and anechoic coatings. Improved performance dictates the use of large-area sensor arrays, with many more processing channels and "smarter" processing algorithms such as adaptive or high-resolution processing at the front end of the system and image processing methods at the display end. In addition, operational systems require fault tolerance, comprehensive online monitoring and maintenance facilities, reconfigurability and improved development aids. An increase in processing throughput of two or three orders of magnitude over current systems is necessary to provide these functions. Advances in semiconductor and integrated-circuit technology promise significant improvements in device performance over the next decade, but it is unlikely that these alone will provide the necessary increase in systems performance. Comparable improvements are required in the areas of algorithm development and system architecture if the capabilities of the advanced technologies currently being developed in various national VHPIC and VHSIC programmes are to be fully exploited. This chapter briefly reviews some aspects of recent developments in these fields and their impact on digital signal processing systems in future sonar applications.
High throughput sonar processors, Page 1 of 2
< Previous page Next page > /docserver/preview/fulltext/books/te/pbte013e/PBTE013E_ch22-1.gif /docserver/preview/fulltext/books/te/pbte013e/PBTE013E_ch22-2.gif