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Memristor-based multiplier designs

Memristor-based multiplier designs

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This chapter presents contributions in the design and implementation of memristor based multipliers. Minimal prior work exists for memristor-based designs for multipliers. The complexity of these designs coupled with the complexity of memristor models and their programming leads to a high design overhead. However, there have been a few prior works that have explored multipliers in the context of memristors for the IMPLY approach. Similar to Chapter 6 on adders, the focus is on four different multipliers: shiftand-add, Booth, array, and Dadda multipliers. For each multiplier, implementations using IMPLY, hybrid-CMOS, threshold gate, and MAD approaches are examined. Each implementation is explained and analyzed in terms of complexity and delay. Due to the increasing complexity of these designs, the CSTG threshold gate implementations are not considered. The component area of CSTG implementations precludes them from being desirable for these units. Recall that a single threeinput CSTG threshold gate requires three memristors, three resistors, and ten MOSFETs. Thus, for some of the more complex designs, only the GOTO pair implementations are presented. Complete schematics and simulations are also given.

Chapter Contents:

  • 7.1 Shift-and-add multipliers
  • 7.1.1 IMPLY shift-and-add multiplier
  • 7.1.1.1 Shift-register implementation
  • 7.1.1.2 Baseline multiplier implementation
  • 7.1.1.3 General optimizations
  • 7.1.1.4 Optimizations for the memristor context
  • 7.1.2 Hybrid-CMOS shift-and-add multiplier
  • 7.1.3 Threshold-gate shift-and-add multiplier
  • 7.1.4 MAD gate shift-and-add multiplier
  • 7.1.4.1 Removal of the shift registers
  • 7.1.4.2 Removal of the sum memristors
  • 7.1.4.3 Pipelining
  • 7.1.5 Shift-and-add multiplier analysis and comparison
  • 7.1.6 IMPLY and MAD Booth multipliers
  • 7.1.6.1 IMPLY Booth multiplier implementation
  • 7.1.6.2 MAD Booth multiplier implementation
  • 7.1.6.3 Booth multiplier comparisons
  • 7.2 Array multipliers
  • 7.2.1 IMPLY array multiplier
  • 7.2.1.1 Optimized implementation
  • 7.2.1.2 Pipelining
  • 7.2.2 Hybrid-CMOS array multiplier
  • 7.2.3 Threshold-gate array multiplier
  • 7.2.3.1 GOTO implementation
  • 7.2.3.2 CSTG implementation
  • 7.2.4 MAD gate array multiplier
  • 7.2.5 Array multiplier analysis and comparison
  • 7.3 Dadda multipliers
  • 7.3.1 IMPLY Dadda multiplier
  • 7.3.2 Hybrid-CMOS Dadda multiplier
  • 7.3.3 Threshold gate Dadda multiplier
  • 7.3.3.1 Counter structure
  • 7.3.3.2 Minnick method for counters
  • 7.3.3.3 Kautz method for counters
  • 7.3.3.4 Counter comparison
  • 7.3.4 MAD gate Dadda multiplier
  • 7.3.4.1 Challenges to pipelining
  • 7.3.5 Dadda multiplier analysis and comparison

Inspec keywords: CMOS logic circuits; memristors; multiplying circuits; MOSFET; resistors; logic gates; integrated circuit modelling; circuit complexity

Other keywords: booth multiplier; array multiplier; MOSFET; dadda multiplier; single threeinput CSTG threshold gate approach; memristor-based multiplier design; shift and-add multiplier; resistor; GOTO; hybrid-CMOS approach; IMPLY approach; adder; MAD approach

Subjects: Insulated gate field effect transistors; CMOS integrated circuits; Resistors; Semiconductor integrated circuit design, layout, modelling and testing; Logic circuits

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