Memristor-based multiplier designs
This chapter presents contributions in the design and implementation of memristor based multipliers. Minimal prior work exists for memristor-based designs for multipliers. The complexity of these designs coupled with the complexity of memristor models and their programming leads to a high design overhead. However, there have been a few prior works that have explored multipliers in the context of memristors for the IMPLY approach. Similar to Chapter 6 on adders, the focus is on four different multipliers: shiftand-add, Booth, array, and Dadda multipliers. For each multiplier, implementations using IMPLY, hybrid-CMOS, threshold gate, and MAD approaches are examined. Each implementation is explained and analyzed in terms of complexity and delay. Due to the increasing complexity of these designs, the CSTG threshold gate implementations are not considered. The component area of CSTG implementations precludes them from being desirable for these units. Recall that a single threeinput CSTG threshold gate requires three memristors, three resistors, and ten MOSFETs. Thus, for some of the more complex designs, only the GOTO pair implementations are presented. Complete schematics and simulations are also given.
Memristor-based multiplier designs, Page 1 of 2
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