Dividers are commonly found in floating point units. These arithmetic units are not only found in standard computing systems but also in high-performance computing as well. Similar to the presented adders and multipliers in the previous two chapters, design constraints, system characteristics, and expected applications all affect the selection of the optimal divider implementation. Sometimes, a simpler, slower divider is preferred and sometimes a more complex, faster divider is. This chapter presents three dividers that represent varying complexity and speed: binary restoring dividers; Sweeney, Robertson, and Tocher (SRT) dividers; and Goldschmidt dividers. The CMOS design for each of these dividers is explained and analyzed in terms of speed and area.

Chapter Contents:

• 5.1 Binary restoring dividers
• 5.2 SRT dividers
• 5.3 Goldschmidt dividers

Inspec keywords: dividing circuits; arithmetic; integrated circuit design; CMOS logic circuits

Other keywords: Goldschmidt divider; CMOS design; divider arithmetic unit; multiplier; Sweeney-Robertson-Tocher divider; adder; SRT divider; floating point unit; standard computing system; binary restoring divider

Subjects: Logic and switching circuits; Logic circuits; Semiconductor integrated circuit design, layout, modelling and testing; CMOS integrated circuits