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Multiplier arithmetic units

Multiplier arithmetic units

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Multipliers are becoming ubiquitous in modern computing systems. With the drive for big data and machine-learning applications, multipliers have become an underlying construct for nearly all state-of-the-art workloads. Depending on the specific system, design constraints, and expected application, the optimal multiplier implementation can vary. Sometimes, a simpler, slower multiplier is preferred and sometimes a more complex, faster multiplier is. This chapter presents four popular multipliers, which span these two metrics: shift-and-add multipliers, Booth multipliers, array multipliers, and Dadda multipliers. The performance and area of these designs are each analyzed in the CMOS domain.

Chapter Contents:

  • 4.1 Shift-and-add multipliers
  • 4.1.1 Booth multiplier
  • 4.2 Array multipliers
  • 4.3 Dadda multipliers

Inspec keywords: multiplying circuits; CMOS logic circuits

Other keywords: CMOS domain; Booth multipliers; array multipliers; multiplier arithmetic units; Big Data; shift-and-add multipliers; design constraints; machine-learning; computing systems; Dadda multipliers

Subjects: Logic circuits; CMOS integrated circuits; Logic and switching circuits

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