eGaN HEMTs gate drivers

eGaN HEMTs gate drivers

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A three-level driving circuit is proposed for eGaN control HEMTs with multi-MHz. The mid-level voltage reduces the reverse conduction loss before ZVS turn-on interval by reducing the reverse conduction voltage since that the source-to-drain voltage decreases when the gate voltage increases. The driving circuit layout and driving resistance selection are investigated to quantitatively analyze the negative gate bias requirement to prevent the false turn-on. The proposed driving circuit can reduce the high reverse conduction loss using the constructed positive gate bias, while achieve desired dv/dt immunity. The proposed driving circuit is applied to a 7 MHz isolated resonant SEPIC converter. With 24 V input and 5 V/10 W output, the driving circuit improves the efficiency of 0.7% (from 72.7% without the mid-level voltage to 73.4% with the mid-level voltage) over the conventional driving circuit.

Chapter Contents:

  • 7.1 Three-level gate drivers
  • 7.1.1 Introduction
  • 7.1.2 Driving requirements for eGaN HEMTs in resonant SEPIC converters
  • Multi-MHz isolated resonant SEPIC converter
  • Reverse conduction mechanism
  • Control HEMT driving consideration
  • SR HEMT driving consideration
  • 7.1.3 Proposed three-level gate drivers for eGaN HEMTs
  • Proposed eGaN control HEMTs three-level driving circuit
  • Proposed driving circuit for eGaN SR HEMTs
  • 7.1.4 Operation principle of three-level gate driver
  • Operation principle
  • Negative gate bias during turn-off transition
  • Design example of control HEMT driving circuit
  • 7.1.5 Rectifier mathematic modeling and design
  • Determine component initial value in wave-shape circuit
  • Rectifier mathematic modeling
  • Design example of C2 and Vref
  • 7.1.6 Experimental results and discussion
  • Control HEMT three-level driving circuit
  • SR HEMT driving circuit
  • 7.2 A digital adaptive driving scheme for eGaN HEMTs in VHF converters
  • 7.2.1 Introduction
  • 7.2.2 Gate-drive challenges for eGaN VHF converters
  • VHF class Φ2 resonant flyback converter
  • Gate-drive timing challenge over input voltage range
  • 7.2.3 Proposed digital adaptive driving scheme
  • Implementation of digital adaptive driving circuit
  • Proposed high time resolution circuit
  • 7.2.4 Relationship analysis between gate-drive timing and input voltage
  • State-space modeling of VHF class Φ2 resonant flyback converter
  • Relationship between gate-drive timing and input voltage
  • 7.2.5 Air-core transformer design
  • 7.2.6 Experimental results and discussion
  • Gate-drive signals with proposed high time resolution circuit
  • VHF flyback with proposed driving scheme
  • 7.3 Summary
  • References

Inspec keywords: driver circuits; circuit layout; zero voltage switching; III-V semiconductors; high electron mobility transistors; gallium compounds; wide band gap semiconductors

Other keywords: positive gate bias; driving circuit layout; eGaN HEMTs gate drivers; isolated resonant SEPIC converter; voltage 24 V; source-to-drain voltage; midlevel voltage; negative gate bias; three-level driving circuit; eGaN control HEMTs; reverse conduction voltage; efficiency 0.7 percent; frequency 7 MHz; reverse conduction loss; dv/dt immunity; multiMHz; ZVS turn-on interval; driving resistance selection

Subjects: Power electronics, supply and supervisory circuits; Other field effect devices

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