eGaN HEMTs gate drivers
A three-level driving circuit is proposed for eGaN control HEMTs with multi-MHz. The mid-level voltage reduces the reverse conduction loss before ZVS turn-on interval by reducing the reverse conduction voltage since that the source-to-drain voltage decreases when the gate voltage increases. The driving circuit layout and driving resistance selection are investigated to quantitatively analyze the negative gate bias requirement to prevent the false turn-on. The proposed driving circuit can reduce the high reverse conduction loss using the constructed positive gate bias, while achieve desired dv/dt immunity. The proposed driving circuit is applied to a 7 MHz isolated resonant SEPIC converter. With 24 V input and 5 V/10 W output, the driving circuit improves the efficiency of 0.7% (from 72.7% without the mid-level voltage to 73.4% with the mid-level voltage) over the conventional driving circuit.
eGaN HEMTs gate drivers, Page 1 of 2
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