In this chapter we will consider means which have been proposed to ease the task of checking the output response when under test, so that the very large number of individual 0 or 1 output bits do not have to be compared step by step against the expected (fault-free) response. Again we shall largely be considering combinational circuits rather than sequential, the latter still requiring their own special testing consideration. Some of the concepts that we will review in this chapter have yet to be reflected in common practice, but all are part of the whole research and development effort which has taken place and still continues on testing strategies.

Inspec keywords: combinational circuits; VLSI; integrated circuit testing

Other keywords: combinational circuits; VLSI testing

Subjects: Semiconductor integrated circuit design, layout, modelling and testing