This chapter considers several strategies for generating tests for digital circuits which, with the noticeable exception of I _DDQ testing involve the monitoring of the 0 and 1 primary output response to appropriate input test vectors. By far the greatest development effort has been concerned with combinational logic. Roth's D-algorithm forms the basis of many automatic test pattern generation programs, but the computational effort in producing ATPG programs for the increasing size and complexity of present-day VLSI circuits is becoming prohibitive. This has forced an increasing interest in other means of test pattern generation, which usually involves some partitioning of the circuit at the design stage so as to allow exhaustive, non exhaustive or pseudorandom test patterns to be used.

Inspec keywords: logic testing; VLSI; logic design; automatic test pattern generation; combinational circuits

Other keywords: combinational logic; Roth's D-algorithm; digital test pattern generation; digital circuit; pseudorandom test pattern; VLSI circuit; design stage; automatic test pattern generation program

Subjects: Digital circuit design, modelling and testing