access icon free Appendix C: Fabrication and yield

Author(s): Stanley L. Hurst
Source: VLSI Testing: digital and mixed analogue/digital techniques, p. 523-526
Publication date January 1998

In Chapter 1 it was shown that the defect level, DL, after test was given by the theoretical relationship DL={1 - Y(1 - FC)} x 100 %. Both the 'goodness' of the fabrication process, the yield, Y, and the effectiveness of the testing procedure, FC, are involved in this result. Modelling of the number of good die on a wafer, which is principally dependent upon die size and process goodness and not upon circuit complexity, has been extensively studied, since with accurate modelling the yield, and hence the cost, of new circuits may be forecast. Also, once the detailed modelling parameters have been determined, the quality of the production lines can be maintained and possibly improved. However, the available modelling theory and available parameter values usually lag the latest production process, and as a result the yield of most production lines has historically tended to be higher than that predicted by modelling theory. (This is also true of reliability predictions for most products, where actual reliability, except for catastrophic occurrences, tends to be somewhat higher than predicted).

Inspec keywords: integrated circuit testing; integrated circuit yield; mixed analogue-digital integrated circuits; VLSI

Other keywords: mixed analogue-digital technique; fabrication process; wafer yield; yield modelling; production line; VLSI testing; circuit cost forecasting

Subjects: Mixed analogue-digital circuits

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