Stanford's ultra-low-power CMOS technology and applications
Stanford's approach to low-voltage CMOS shows that, without speed performance loss, significant power reductions are achieved after modifying CMOS processes to accommodate low, tuneable thresholds. A key concept is to balance the leakage power of inactive circuits with the switching power of the circuits doing the work. This requires electrical adjustment of threshold voltages and new circuit design techniques. Electrically tuneable thresholds can accommodate a wide range of applications and activity levels in a system, and can significantly improve worst case performance at low voltage. Well and substrate ties are separated from supply rails and controlled to compensate for process and ambient variations. An implementation of a self tuning system using low/tuneable threshold devices in a VLSI environment was shown. For the same switching speed, fabricated devices show significant reduction in switching power when compared to standard devices operated at a higher supply voltage. Cryogenic ULP techniques allow for insight into deep submicron effects and allow the same performance of standard 5V CMOS to be achieved at 330mV, for 1/230 of the energy. The key to high performance at low voltage is low or near-zero threshold. This requires room temperature thresholds of about -200mV for maximum performance at 77K. ULP techniques are only in their infancy and yet they have already provided a very good opportunity for increased levels of interaction among process, device, circuit and system engineers towards optimum low power microelectronic solutions.