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Matched delay technique for high-speed digital design

Matched delay technique for high-speed digital design

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This chapter describes the matched delay technique and its applications. First, the fundamental concepts of matched delay design are described. Next, we discuss several practical issues that must be considered in matched delay system designs. Finally, three fabricated designs using the matched delay technique are presented. The matched delay technique was employed in developing a high-performance digital sampler with 1 Gbit/s bandwidth and 25ps resolution in a MOSIS 1.2μm CMOS process. The matched delay sampler implements the demultiplexing function of a network interface by performing a serial-to-parallel conversion on an incoming data stream. In addition, this device is a core component in another matched delay design, a data recovery circuit.

Inspec keywords: CMOS digital integrated circuits; delay circuits; high-speed integrated circuits; analogue-digital conversion; demultiplexing equipment; network interfaces

Other keywords: serial-to-parallel conversion; matched delay system design; data recovery circuit; high-performance digital sampler; demultiplexing function; high-speed digital design; network interface; MOSIS CMOS process; size 1.2 mum; bit rate 1 Gbit/s

Subjects: Digital circuit design, modelling and testing

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