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Ultra-low-power digital design

Ultra-low-power digital design

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This chapter discusses design methodologies for ultra-low-power (ULP) CMOS circuits at different abstraction levels, namely system, architectural, logic, design, and layout. The main techniques to reduce power consumption are introduced such as reduction of circuit activity, operating frequency, switched capacitances and supply voltages. Low-voltage and low-power techniques for microprocessors are reviewed, including cache and interleaved memories. Previous chapters have introduced ULP techniques and possibilities for advanced processes with extremely low supply and threshold voltages. This chapter exploits techniques to achieve ULP consumption without aggressively changing processes. Many opportunities for reducing power consumption at a given throughput are opened by appropriately combining the ULP techniques presented here.

Inspec keywords: integrated circuit design; CMOS digital integrated circuits; low-power electronics

Other keywords: abstraction levels; architectural level; logic level; power consumption; design level; CMOS circuits; circuit activity; system level; ultra-low-power digital design; interleaved memories; cache memories; layout level

Subjects: Digital circuit design, modelling and testing

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