High-speed and low-power techniques in CMOS and BiCMOS

High-speed and low-power techniques in CMOS and BiCMOS

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This chapter discusses the potential of CMOS and BiCMOS to obtain high speed and low power. It demonstrates that CMOS technologies of today have the ability to approach 1 GHz clock frequencies. By combining CMOS with bipolar transistors, using a BiCMOS process, we may combine very high data rates (< 40 Gb/s) and very high complexity (using CMOS) in a single chip. It discusses the possibility to reduce power in CMOS circuits and showed that considerable power reduction can be obtained by sacrificing clock frequency (not necessarily sacrificing computing capacity). Also demonstrates the possibility to reduce power considerably, with no or very little reduction in clock frequency through process reoptimisation. These results may be interesting enough to affect process generations coming along. Finally it discusses the future development of CMOS technology and concluded that CMOS has very much more to give.

Inspec keywords: BiCMOS integrated circuits; bipolar transistors; low-power electronics; CMOS integrated circuits

Other keywords: process reoptimisation; BiCMOS process; bipolar transistors; CMOS technologies; low-power techniques; power reduction; clock frequency reduction; high-speed techniques

Subjects: CMOS integrated circuits

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