Fault modelling and simulation for the test of integrated analog and mixed-signal circuits

Access Full Text

Fault modelling and simulation for the test of integrated analog and mixed-signal circuits

For access to this article, please select a purchase option:

Buy chapter PDF
£10.00
(plus tax if applicable)
Buy Knowledge Pack
10 chapters for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Low-power HF Microelectronics: a unified approach — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Author(s): Michael J. Ohletz 1
View affiliations
Source: Low-power HF Microelectronics: a unified approach,1996
Publication date January 1996

This chapter describes test strategies, including a concise introduction to DSP testing, for analog and mixed-signal circuits. The main emphasis will be on integrated circuits. Although design-for-testability and design-for diagnosibility are only briefly reviewed, two self-test schemes for mixed-signal ICs are presented in more detail describing the necessary components along with implementations for the on-chip generation of test stimuli . Some prerequisites for automatic fault simulation of analog circuits are dealt with. Fault models for analog circuits are discussed and the local layout realistic faults mapping scheme which allows more realistic fault models to be obtained prior to the final layout is introduced. Appropriate simulation fault models are discussed along with a brief description of the automatic fault simulation tool AnaFAULT and the fault extraction tool LIFT.

Inspec keywords: analogue integrated circuits; design for testability; automatic test software; fault simulation; mixed analogue-digital integrated circuits; integrated circuit testing

Other keywords: LIFT fault extraction tool; on-chip generation; AnaFAULT automatic fault simulation tool; local layout realistic faults mapping; analog integrated circuit test; mixed-signal circuits; design-for-testability; design-for diagnosibility; fault modelling; DSP testing

Subjects: Analogue circuit design, modelling and testing

Preview this chapter:
Zoom in
Zoomout

Fault modelling and simulation for the test of integrated analog and mixed-signal circuits, Page 1 of 2

| /docserver/preview/fulltext/books/cs/pbcs008e/PBCS008E_ch13-1.gif /docserver/preview/fulltext/books/cs/pbcs008e/PBCS008E_ch13-2.gif

Related content

content/books/10.1049/pbcs008e_ch13
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading