Designing testable VLSI devices presents a continuous challenge to VLSI full-custom designers. Design-for-testability (DFT) has emerged as an integral part of the design process, but the integration can only be achieved if the right tools are in place. In this chapter we discuss the concepts of macro-testability and present the underlying tools to allow designers of VLSI devices to implement the testability structures required by macro-testability. These tools are now in use within Philips and the chapter concludes with comment on the practical application of such techniques.

Inspec keywords: design for testability; VLSI; circuit testing

Other keywords: design-for-testability; VLSI testable-design technique; macro-testability; testability structures; testable VLSI device; VLSI full-custom designer

Subjects: Semiconductor integrated circuit design, layout, modelling and testing