This chapter has described some current knowledge based systems to aid design for testability, and described research in this area taking place at Brunei University. It has also attempted to highlight specific problem areas in test strategy planning, and presented an economics based approach to the problem of test strategy evaluation. The system described here was constructed as a research tool, but the concepts and test strategy planning methods were used in a current ESPRIT project for gate array test strategy planning, which is now under industrial evaluation (Dislis et al, 1991). The basis of the test strategy planner is the cost modelling employed, which the authors believe is a reliable method for making realistic comparisons of design for test methodologies. The results of the economics based planning have so far agreed with test experts' approaches.

Inspec keywords: logic testing; logic arrays; integrated circuit testing; integrated circuit design; design for testability; knowledge based systems; logic design

Other keywords: test strategy evaluation; economic-based approach; industrial evaluation; design for testability; gate array test strategy planning; ESPRIT project; knowledge-based test strategy planning; Brunei University; cost modelling

Subjects: Logic circuits