This chapter describes CAD techniques capable of synthesising Fast Discrete Cosine Transform (FDCT) Blocks from behavioural, or algorithmic, specifications. We introduce SAVAGE (a Simulated Annealing based VLSI Architecture GEnerator), a software tool developed under the auspices of the Silicon Architectures Research Initiative (S ARI(Grant, 1990)) hosted at the University of Edinburgh. SAVAGE is capable of taking a data-flow description of an input algorithm, and applying a number of synthesis steps, or transformations, to produce a hardware netlist of a datapath. The netlist description is then passed to logic synthesis and layout tools to complete the route to silicon. These application specific synthesis steps are controlled by the computational technique known as simulated annealing. This chapter reviews the design process, from the initial high-level description of the FDCT, through the various synthesis transformations, and presents a set of test results illustrating the flexibility of the SAVAGE software. Finally, some extensions to the prototype SAVAGE system are described.

Inspec keywords: discrete cosine transforms; circuit CAD; VLSI; high level synthesis; simulated annealing

Other keywords: software tool; netlist description; logic synthesis; CAD technique; prototype SAVAGE system; SAVAGE software; fast discrete cosine transform blocks; synthesis transformation; datapath; algorithmic; simulated annealing based VLSI architecture generator; data-flow description; simulated annealing based synthesis

Subjects: Computer-aided circuit analysis and design