An expert systems approach to analogue VLSI layout
The production of computer-aided design tools and environments for analogue VLSI circuit layout has proved very much more difficult than in the digital domain. The principal reason for this is that analogue circuit design involves the accommodation of many, often conflicting, practical constraints (Allen, 1986). Typical of these constraints are the optimum placement of circuit components, layout of large transistors, routing of interconnection channels noting the importance of avoiding signal cross talk, and the minimisation of parasitics which might affect circuit performance (Haskard and May, 1988, Kimble et al, 1985 and Serhan, 1985). In addition, the design of analogue circuits requires precision modelling of individual components and extensive simulation to verify the desired performance (Rijmenants, 1988). The problems associated with analogue VLSI layout techniques are reasonably well understood by experienced analogue circuit designers and it is widely accepted that these problems cannot be solved purely algorithmically. To produce a sophisticated analogue VLSI layout design tool which will enable these demanding multiple-constraint problems to be solved effectively, requires the efficient incorporation of design expertise as an integral part of the automatic analogue VLSI layout design tool. The purpose of this work is essentially to make a contribution towards meeting these demands, and to provide a greater understanding of typical expert layout design rules and how they should be incorporated within the Expert Analogue Layout System (EALS).
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