This chapter considers a flexible framework for the automatic synthesis of data conversion architectures employing binary-weighted C-arrays which can meet a broad range of input specifications, both for A/D and D/A conversion, and perform to a high degree of precision even when considering the non-idealities of the circuit components such as offset, charge injection, noise and component mismatch errors. This included not only the description of the complete architecture design and verification automation processes but also the discussion of an efficient top-down flow of design information to access a variety of lower level design environments including cell libraries, parametrized circuit module generators and circuit level compilers. By ensuring such design flexibility at the lower level, this framework also renders it easier to meet even the stringent specifications for implementation of a data conversion system employing binary-weighted C-arrays.

Inspec keywords: data conversion; high level synthesis

Other keywords: design flexibility; verification automation process; top-down flow; flexible framework; cell libraries; binary-weighted C-arrays; automated high level synthesis; data conversion system; design information; data conversion architecture; A/D conversion; circuit component; automatic synthesis; circuit level compiler; D/A conversion; parametrized circuit module generator; architecture design

Subjects: Computer-aided circuit analysis and design