This chapter includes all design files (schematics, state machines and constraint files, all summarised in Section C. 1) for the FPGA based component of our design. Please remember that this is one of the first prototype designs, so while the design works, it should not be considered to be the 'best possible' implementation. No floor planning (beyond specifying which I/O pins to use) was performed in this design the final FPGA layout is entirely the result of automated tools. This implementation is targeted to the Xilinx Virtex XCV800 BG432 FPGA, and in particular, to the GatesMaster BITSI daughterboard (manufactured by Lyr Signal Processing [143]) using this FPGA. Naturally, this design will reflect the particular hardware we have used, particularly for I/O blocks, however, our design is quite modular so you should easily be able to modify the design to work with your hardware.
Appendix C: FPGA design, Page 1 of 2
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