Our design makes use of the SDRAM241 available on the Gatesmaster/SignalMaster board used in this work. This appendix details the tuning used to access that memory. This appendix is not intended as a tutorial on the use of SDRAM (see Reference 274 for a useful introduction) but rather to clarify the timing used in the design of our FPGA. We access SDRAM using single word bursts and a CAS latency of 2.
Appendix B: SDRAM timing, Page 1 of 2
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