access icon free Appendix B: SDRAM timing

Author(s): J. Kolodko  and  L. Vlacic
Source: Motion Vision: design of compact motion sensing solutions for navigation of autonomous systems, p. 297-300
Publication date January 2005

Our design makes use of the SDRAM241 available on the Gatesmaster/SignalMaster board used in this work. This appendix details the tuning used to access that memory. This appendix is not intended as a tutorial on the use of SDRAM (see Reference 274 for a useful introduction) but rather to clarify the timing used in the design of our FPGA. We access SDRAM using single word bursts and a CAS latency of 2.

Inspec keywords: DRAM chips; timing circuits; field programmable gate arrays

Other keywords: SDRAM timing; single word burst; memory access; CAS latency; gatesmaster-signalmaster board; FPGA

Subjects: Memory circuits

Preview this chapter:
Zoom in
Zoomout

Appendix B: SDRAM timing, Page 1 of 2

| /docserver/preview/fulltext/books/ce/pbce067e/PBCE067E_appendixb-1.gif /docserver/preview/fulltext/books/ce/pbce067e/PBCE067E_appendixb-2.gif

Related content

content/books/10.1049/pbce067e_appendixb
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading