Our design makes use of the SDRAM²⁴¹ available on the Gatesmaster/SignalMaster board used in this work. This appendix details the tuning used to access that memory. This appendix is not intended as a tutorial on the use of SDRAM (see Reference 274 for a useful introduction) but rather to clarify the timing used in the design of our FPGA. We access SDRAM using single word bursts and a CAS latency of 2.

Inspec keywords: DRAM chips; timing circuits; field programmable gate arrays

Other keywords: SDRAM timing; single word burst; memory access; CAS latency; gatesmaster-signalmaster board; FPGA

Subjects: Memory circuits