Inspec keywords: CMOS logic circuits; comparators (circuits); calibration; circuit optimisation; logic design; compensation; flip-flops; integrated circuit design; low-power electronics

Other keywords: design optimisation procedure; size 0.18 mum; latch comparator; calibration resolution; simple digital sequencer; digital mismatch compensation; word length 7.0 bit; post-layout statistical simulations; reduced power consumption; comparator performance; complementary metal–oxide–semiconductor technology; dynamic comparators; three-step design procedure; calibration control; calibration accuracy; digital calibration schemes; word length 5.9 bit; high-speed operation

Subjects: Logic and switching circuits; Logic design methods; Digital circuit design, modelling and testing; Semiconductor integrated circuit design, layout, modelling and testing; CMOS integrated circuits; Logic circuits