Inspec keywords: neural chips; integrated circuit interconnections

Other keywords: geometric scaling; manufacturing process; biological self-repair computational model; global self-repair process; astrocyte cells; communication infrastructure; hardware reliability; faulty synapse connections; astrocyte communication; on-chip communication; neuro-glia network mapping; neural networks; local communication mechanism; astrocyte-driven repair process; scalable communication interconnect; synaptic activity regulation; global astrocyte network

Subjects: Neural nets (circuit implementations); Neural net devices